Go to the first, previous, next, last section, table of contents.


MIL-STD-1750 Dependent Features

M1750 Options

The MIL-STD-1750 version of m1750-coff-as has a few machine dependent options.

m1750-coff-as can assemble code for several different members of the MIL-STD-1750A/B family. The default depends upon how m1750-coff-as was configured when it was built; normally, the default is to assemble code for the 1750A. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the MIL-STD-1750 family are very similar. For detailed information about the differences, see MIL-STD-1750B, or 1750 vendor's literature.

`-A1750a'
Assemble for the 1750a with no expanded memory. (the default)
`-A1750b'
Assemble for the 1750b with all instruction options but no expanded memory.
`-Ama31750'
Assemble for the GEC-Plessey MA31750 in 1750B mode.
`-Amas281'
Assemble for the GEC-Plessey MAS281 or McDonnell Douglas MDC281.
`-Ammu'
Support expanded memory.
`-Ano-mmu'
Do not support expanded memory.
`-Ab1'
Permit 1750B optional mathematical instructions.
`-Ab2'
Permit 1750B optional long loads and stores.
`-Ab3'
Permit 1750B optional unsigned arithmetic and load and store byte instructions.
`-Ano-b1'
Reject 1750B optional mathematical instructions.
`-Ano-b2'
Reject 1750B optional long loads and stores.
`-Ano-b3'
Reject 1750B optional unsigned arithmetic and load and store byte instructions.

Syntax

The MIL-STD-1750 version of m1750-coff-as uses instructions names and syntax as defined in the standard. Directives follow the m1750-coff-as conventions.

The names of the registers are: r0, r1, r2, r3, r4, r5, r6, r7, r8. r9, r10, r11, r12, r13, r14, r15. The assembler also accepts an upper case letter R. The registers r1 to r15 may be used as index registers. The registers r12 to r15 may be used as base registers.

The following addressing modes are understood. Note that address will be converted into word adddesses when used in an instruction.

Register Direct
`lr register,register'
Memory Direct
`l word-address'
Memory Direct Indexed
`l word-address,index-register'
Memory Indirect
`li address'
Memory Indirect with Pre-Indexing
`li word-address,index-register'
Immediate Long
`lim number'
Immediate Short Positive
`lisp short-number'
Immediate Short Negative
`lisn short-number'
Instruction Counter Relative
`br word-displacement'
Base Relative
`lb base-register,offset'
Base Relative Indexed
`lb base-register,offset,index-register'
Special
`nop'

Floating Point

The floating and fixed point formats generated by directives are these.

.float
Single precision floating point constants (See MIL-STD-1750A section 4.1.5).
.double
Double precision floating point constants (See MIL-STD-1750A section 4.1.6).

M1750 Machine Directives

.skip number

.skip is indentical to the .space directive.

.rdata subsection

.rdata tells m1750-coff-as to assemble the following statements onto the end of the read-only data subsection numbered subsection (which is an absolute expression). If subsection is omitted, it defaults to zero.

.rodata subsection

.rdata is identical to a .rdata directive.

.sbam flonums

.sbam expects one or more flonums, separated by commas. It assembles Single precision binary angular measurement (See MIL-STD-1750B section 4.1.11).

.dbam flonums

.dbam expects one or more flonums, separated by commas. It assembles Double precision binary angular measurement (See MIL-STD-1750B section 4.1.12).

Opcodes

index M1750 opcodes index opcodes, M1750 index instruction set, M1750

Extended Floating Load Register

The 1750 does not have the important load register instruction for extended precision floating point. The reason is we can copy a 3-word extended floating point value from one triple register to another using a single load register and a double load register. However if the source triple and destination triples overlap, then it is important to get the single and double load in the correct order otherwise the source will be overwritten before it is completely copied.

The opcode "eflr" is translated by the assembler into either a single load followed by a double load, or a double load followed by a single load, depending on which registers are used, and guarantees correct operation.

Note that the condition codes will not be correctly set by eflr. To set the condition codes you should do an extended compare with zero. Of course to check whether a number is negative or not, no matter whether it is a 16 bit, 32 bit or 48 bit, fixed or floating, you only have to test the sign bit of the first word.

Expanded Memory Support

There are two macro-like instructions, LSJS and LURS, for supporting subprogram call and return across address states. Normally these will be translated by the assembler into SJS and URS instructions, but if the assembler is run with the expanded memory option -Ammu then LSJS is expended into an sequence of instructions that makes a call to a subprogram that may be in a different address state. The LURS instruction is converted into a LST instruction, using the register given in the LURS instruction (usually R15), and an offset of zero.

Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting `j' for `b' at the start of a 1750 mnemonic.

The following table summarizes the pseudo-operations.

+-----------+----------+--------------+
| Pseudo    |    Instruction size     |
| Op        | 16 bits  |  32 bits     |
+-----------+----------+--------------+
| j    L1   | br   L1  |  jc   uc,L1  |
| jeq  L1   | beq  L1  |  jc   eq,L1  |
| jne  L1   | bne  L1  |  jc   ne,L1  |
| jgt  L1   | bgt  L1  |  jc   gt,L1  | 
| jlt  L1   | blt  L1  |  jc   lt,L1  |
| jge  L1   | bge  L1  |  jc   ge,L1  |
| jle  L1   | ble  L1  |  jc   le,L1  | 
+-----------+----------+--------------+

XIO Commands

All the MIL-STD-1750A and 1750B XIO commands are supported.

BIT, CC, CI, CLC, CLIR, CO, DMAD, DMAE, DSBL, DSUR, ENBL, ESUR, GO, ICW, ITA, ITAR, ITB, ITBR, ITGI, LMP, LOS, LXMP, MPEN, OD, OTA, OTAR, OTB, OTBR, OTGR, PI, PO, RCFR, RCS, RCW, RDI, RDOR, RDOW, RFMK, RFR, RIC1, RIC2, RIPR, RLP, RMFA, RMFP, RMFS, RMK, RMP, RNS, ROPR, ROS, RPBS, RPI, RPIR, RPS, RSW, RXMP, SFMK, SFR, SMK, SPI, TAH, TAS, TBH, TBS, TPIO, WIPR, WOPR, WPBS, WSW

Special Characters

The line-comment character is `!'. If a `#' appears at the beginning of a line, it is treated as a comment unless it looks like `# line file', in which case it is treated normally.

@raisesections


Go to the first, previous, next, last section, table of contents.